There is a DRAM used as a semiconductor memory representing a large capacity memory. The memory capacity of this DRAM is increasing more and more, and, under the circumstances, it has become necessary to reduce the area occupied by the memory cells to improve the degree of integration of the DRAM.
However, the storage capacity of an information storing capacity element (capacitor) in DRAM memory cells must be fixed to a certain value regardless of the generation when in taking the DRAM operation margin, software errors, etc. into consideration. Generally, it is known that the storage capacity cannot be reduced proportionally.
This is why there is now under development a capacitor structure that can secure a storage capacity necessary in a limited small occupation area. As such a capacitor structure, for example, there has been adopted a three-dimensional capacitor, such as a so-called stacked capacitor composed of two-layer electrodes composed of polysilicon, etc. and stacked via a capacity insulating film.
A stacked capacitor is generally composed of capacitor electrodes disposed in the upper layer of a memory cell selecting MISFET (Metal Insulator Semiconductor Field Effect Transistor). In this case, a small occupied area can secure a large storage capacity, as well as only a small storage capacity, as needed.
As such a stacked capacitor structure, for example, there are a so-called capacitor over bit-line (hereafter, to be abbreviated as COB) structure, in which a capacitor is disposed over the bit-line, and a capacitor under bit-line (hereafter, to be abbreviated as CUB) structure, in which a capacitor is disposed under the bit-line.
In a DRAM having such a COB/CUB structure, capacitor connecting holes must be formed so that a conductor film or a bit-line in each capacitor connecting hole is not short-circuited with a word-line. Thus, the interval between adjacent word-lines must be widened to cope with connecting hole positioning failures. And, this hinders improvement of the degree of integration of elements, as well as a reduction of the chip sizes. In order to realize high integration, therefore, high technology of positioning and alignment, as well as process management, are needed.
In order to solve these problems and meet certain requirements, there is proposed a technology for forming capacitor connecting holes and bit-line connecting holes by etching in a self-matching manner with respect to the word-lines by covering the top and side surfaces of the word-lines using an insulating material different in type from an interlaminar insulating film, such as a nitride film, etc.
In the case of such a technology, when capacitor connecting holes and bit-line connecting holes are formed by etching, it is possible to prevent the word-lines from being exposed from the connecting holes, even when the connecting holes overlap the word-lines, since the nitride film around the word-lines functions as an etching stopper. Thus, the connecting holes can be formed properly.
The technology for forming capacitor connecting holes and bit-line connecting holes in a self-matching manner with respect to the word-lines is disclosed in the official report of Unexamined Published Japanese Patent Application No. 9-55479.
Under the circumstances, the present inventor has examined the technology for forming the capacitor connecting holes and bit-line connecting holes in a self-matching manner with respect to the word-lines. The following technologies are not well-known, but have been examined by the present inventor. An outline of those technologies will be described below.
The DRAM described above is formed in the following process flow. At first, a conductor layer is formed on a semiconductor substrate via a gate insulating film. On the conductor film there is deposited a first nitride film. Then, the first nitride film and the conductor film are patterned using the same mask to form gate electrodes of the memory cell selecting MISFET and gate electrodes of the peripheral circuit MISFET. At this time, the gate electrodes of plural memory cells disposed in the row direction of the memory cell array are formed unitarily and function as a DRAM word line. Next, a low density semiconductor area is formed for the memory cell selecting MISFET and the peripheral circuit MISFET, respectively, in a self-matching manner with respect to the memory cell selecting MISFET and the peripheral circuit MISFET, respectively. Then, a second nitride film is deposited on the semiconductor substrate and anisotropic etching is carried out to form nitride film side wall spacers on side walls of the gate electrodes of both the memory cell selecting MISFET and the peripheral circuit MISFET. Then, a high density semiconductor area is formed for the peripheral circuit MISFET in a self-matching manner with respect to the side wall spacers. Thereafter, on the semiconductor substrate there is deposited an interlaminar insulating film composed of an oxide film, and bit-line and capacitor connecting holes are opened in the memory cell area in a self-matching manner with respect to word-lines. This process for opening the bit-line and capacitor connecting holes in this interlaminar insulating film is performed on conditions to increase the etching selection ratio of the nitride film composing side walls to the oxide film composing the interlaminar insulating film, so that the bit-line and capacitor connecting holes can be formed without exposing the word-lines.
On the other hand, in order to improve the degree of integration of the DRAM memory cells, the interval between word-lines must be minimized. When the second nitride film is deposited on the word-lines disposed at minimized intervals up to a specified film thickness or more, every space between word-lines in the memory cell area is filled completely with the second nitride film, so that the surface of the semiconductor substrate is not exposed even alter anisotropic etching is carried out for the nitride film to form side wall spacers. Otherwise, a problem that the exposed area is very small and the contact resistance generated between the exposed area and each bit-line or capacitor electrode is increased significantly arises.
In addition, side wall spacers formed on side walls of the gate electrodes of both the memory cell selecting MISFET and the peripheral circuit MISFET determine the length of the low density semiconductor area of the peripheral circuit MISFET having an LDD structure. And, when this side wall spacer is reduced in width, problems arise in that the short channeling effect of the peripheral circuit MISFET becomes remarkable and the punched-through dielectric strength between source and drain is lowered. This is why the second nitride film for forming side wall spacers must have a thickness greater than a specified value.
In other words, in order to secure a specified performance of a MISFET, the LDD structure must be optimized. When the DRAM memory cell selecting MISFET is divided finely to reduce the width of the side wall spacer, the side wall spacer width must be greater than a specified value to prevent the high density semiconductor area of the peripheral circuit MISFET from being distributed over the low density semiconductor area. This means that the width of each side wall spacer has a lower limit.
On the other hand, when the memory array is divided finely, the interval between gate electrodes, that is, the interval between adjacent memory cell selecting MISFETs is narrowed accordingly. Thus, every portion to be connected in a self-matching manner is also reduced in width. When such a connecting area is narrowed, the contact resistance in the area is also increased significantly. Thus, the side wall spacer must be minimized in width. Such a requirement conflicts with a requirement for optimizing the LDD structure. And, in the worst case, when the LDD structure is optimized, adjacent side wall spacers are overlapped in the memory array area so that self-matching connections are disabled.
Under the circumstances, it is an object of the present invention to provide semiconductor integrated circuit technology for dividing DRAM memory cells finely so as to be more highly integrated and to make the operation faster in the semiconductor integrated circuitry provided with a DRAM.
It is another object of the present invention to provide a semiconductor integrated circuit technology for dividing memory cells finely so as to be more highly integrated and make the operation faster in the semiconductor integrated circuitry provided with a DRAM and an electrically reloadable nonvolatile memory.
It is still another object of the present invention to provide a technology for realizing a high performance semiconductor integrated circuit having a DRAM which exhibits excellent refreshing characteristics.
It is still another object of the present invention to provide a technology for realizing a semiconductor integrated circuit that can prevent the element isolating area on the semiconductor substrate from over-etching when opening the connecting holes to improve the reliability of the semiconductor integrated circuitry.
It is still another object of the present invention to provide a technology for simplifying the method of manufacturing a semiconductor integrated circuit provided with a DRAM and an electrically reloadable nonvolatile memory.
It is still another object of the present invention to provide a technology for realizing a semiconductor integrated circuit, which can divide DRAM cells finely so as to be more highly integrated and improve the reliability of the peripheral circuit MISFET.
It is still another object of the present invention to provide a technology for forming connecting holes in a self-matching manner even in a highly integrated DRAM memory cell area and to prevent the element isolating area at the bottom of each of the connecting holes from over-etching.
It is still another object of the present invention to provide a technology for improving the connecting hole treatment margin when the connecting holes are formed in a self-matching manner and for preventing the element isolating area at the bottom of each connecting hole from over-etching.
It is still another object of the present invention to provide a technology for suppressing an increase in the number of processes required when the connecting holes are formed in a self-matching manner and the element isolating area at the bottom of each connecting hole is prevented from over-etching.
It is still another object of the present invention to provide a technology for integrating a semiconductor integrated circuit more highly and for improving the refreshing characteristics of the DRAM and the transistor characteristics of the memory cell area.
The above and other objects and novel features of the present invention will fully appear from the description provided by this specification and from the accompanying drawings.